1. Field of the Invention
The present invention relates to the field of semiconductor fabrication, and more particularly, to a method and apparatus for depositing amorphous and polysilicon films with improved step coverage.
2. Discussion of Related Art
Polysilicon crystalline (polysilicon) and amorphous silicon thin films are used throughout the many semiconductor integrated circuit manufacturing processes. These films are used, for example, in the fabrication of gate electrodes, stack or trench capacitors, emitters, contacts, fuses, and antifuses. As device dimensions decrease to below 0.25 microns in order to increase packing density, aspect ratios (aspect ratio=depth/width) of holes, vias, and trenches in the integrated circuit are also increasing. In order to fill high aspect ratio openings (aspect ratios.gtoreq.to 2.5), deposition processes which are capable of good step coverage (step coverage %=film thickness on a step surface/film thickness on a flat surface.times.100%) are required to ensure complete hole filling without the creation of voids.
One current method which can provide adequate step coverage is low pressure chemical vapor deposition (LPCVD). In LPCVD processes, reaction vessels are evacuated to relatively low pressures of between 100-1000 mtorr. The low pressures associated with LPCVD processes cause silicon films to be deposited at low rates (about 100 angstroms (.ANG.)/minute for undoped films and about 20 .ANG./minute for doped films). The low deposition rates enable the films to be deposited with good step coverage. When n-type dopants are introduced in a LPCVD batch system to produce an insitu doped film, poor step coverage results. Further reducing the deposition rate is necessary to get good step coverage. Although LPCVD processes can form high quality films, their low deposition rates necessitate the processing of multiple wafers (i.e. up to 100) at one time in a batch type reaction vessel. A problem with processing a plurality of wafers in a single machine at a single time is that it is difficult to obtain uniform film thicknesses and dopant compositions from wafer to wafer and from batch to batch. Nonuniformity in film thickness and doping profiles can drastically affect the electrical characteristics of the fabricated film and therefore, the performance and reliability of the fabricated device. Controlling film thickness and sheet resistance uniformity will be an even greater challenge for LPCVD batch systems when wafer size is increased to 300 mm and above.
To fabricate polysilicon and amorphous silicon films with precise thickness and doping uniformity across a wafer and from wafer to wafer, single wafer CVD processes are used. A single wafer CVD process for producing a silicon layer on a silicon wafer is described in U.S. Ser. No. 07/742,954, filed Aug. 9, 1991, entitled Low Temperature High Pressure Silicon Deposition Method and is assigned to the present assignee. In such a process, a pressure between 10-350 torr is achieved and maintained in a reaction chamber. Hydrogen gas at about 10 liters/minutes is fed into the chamber along with less than 525 sccm of silane (SiH.sub.4) (silane partial pressure is less than 4 torr) while the substrate is heated to a temperature of between 600.degree.-750.degree. C. An undoped polysilicon film is deposited under these conditions at a rate of up to about 2000 .ANG./minute. The higher pressure used in the single wafer method increases deposition rate of the polysilicon film. A phosphorous insitu doped polysilicon film can be deposited by including 300 sccm of 1% phosphine (PH.sub.3) in hydrogen (PH.sub.3 partial pressure of about 0.023 torr) into the gas mix and by heating the substrate to a temperature of about 650.degree. C. With such a process, a polycrystalline silicon film containing about 1.5.times.10.sup.21 /cm.sup.3 of phosphorous can be deposited at a rate of up to about 1500 .ANG./minute.
A problem with the above referenced single wafer CVD processes is that step coverage is poor and so cannot be used to fill high aspect ratio openings without causing the formation of voids. Voids can cause reliability problems and failures in the fabricated integrated circuits. Additionally, if dopants are included into the gas mix to form a low resistivity insitu doped silicon film, step coverage becomes even worse.
Thus, what is desired is a method for depositing in a single wafer CVD apparatus and insitu doped silicon film at a high deposition rate and with good step coverage so that high aspect ratio openings can be filled void free in a manufacturable amount of time.